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1 ltc3736-2 37362fa dual 2-phase, no r sense tm , synchronous controller with output tracking high efficiency, 2-phase, dual synchronous dc/dc step-down converter no current sense resistors required out-of-phase controllers reduce required input capacitance tracking function wide v in range: 2.75v to 9.8v 0.6v 1% voltage reference high current limit constant frequency current mode operation low dropout operation: 100% duty cycle true pll for frequency locking or adjustment selectable pulse-skipping/forced continuous operation auxiliary winding regulation internal soft-start circuitry power-good output voltage monitor output overvoltage protection micropower shutdown: i q = 9 a tiny low profile (4mm 4mm) qfn and narrow ssop packages the ltc ? 3736-2 is a 2-phase dual synchronous step-down switching regulator controller with tracking that drives ex- ternal complementary power mosfets using few external components. the constant frequency current mode archi- tecture with mosfet v ds sensing eliminates the need for sense resistors and improves efficiency. power loss and noise due to the esr of the input capacitance are mini- mized by operating the two controllers out of phase. pulse-skipping operation provides high efficiency at light loads. 100% duty cycle capability provides low dropout operation, extending operating time in battery-powered systems. the switching frequency can be programmed up to 750khz, allowing the use of small surface mount inductors and ca- pacitors. for noise sensitive applications, the ltc3736-2 switching frequency can be externally synchronized from 250khz to 850khz. an internal soft-start, which can be lengthened externally, smoothly ramps the output voltage during start-up. the ltc3736-2 is available in the tiny thermally enhanced (4mm 4mm) qfn and 24-lead narrow ssop packages. one or two lithium-ion powered devices notebook and palmtop computers, pdas portable instruments distributed dc power systems sense1 + v in ltc3736-2 sgnd sense2 + tg1 tg2 sw1 sw2 bg1 bg2 pgnd pgnd v fb1 v fb2 220pf v out1 2.5v v out2 1.8v 47 f 47 f 15k 220pf 15k 59k 59k 187k 118k 2.2 h 2.2 h i th1 37362 ta01a i th2 10 f 2 v in 2.75v to 9.8v efficiency and power loss vs load current (figure 15 circuit) features descriptio u applicatio s u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5929620, 6144194, 6580258, 6304066, 6611131, 6498466. load current (ma) 65 efficiency (%) power loss (w) 95 100 60 55 90 75 85 80 70 1 100 1000 10000 37362 ta01b 50 10 0.01 0.1 1 0.001 10 v out = 2.5v efficiency power loss
2 ltc3736-2 37362fa absolute axi u rati gs w ww u electrical characteristics the denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 4.2v unless otherwise specified. parameter conditions min typ max units main control loops input dc supply current (note 4) normal mode run/ss = v in 475 750 a shutdown run/ss = 0v 9 20 a uvlo v in = uvlo threshold C200mv 3 10 a undervoltage lockout threshold v in falling 1.95 2.25 2.55 v v in rising 2.15 2.45 2.75 v wu u package / o rder i for atio consult ltc marketing for parts specified with wider operating temperature ranges. uf part marking ltc3736euf-2 t jmax = 125 c, ja = 37 c/w exposed pad (pin 25) is pgnd must be soldered to pcb order part number t jmax = 125 c, ja = 130 c/ w order part number order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 sw1 iprg1 v fb1 i th1 iprg2 plllpf sgnd v in track v fb2 i th2 pgood sense1 + pgnd bg1 sync/fcb tg1 pgnd tg2 run/ss bg2 pgnd sense2 + sw2 24 23 22 21 20 19 7 8 9 top view 25 uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 i th1 iprg2 plllpf sgnd v in track sync/fcb tg1 pgnd tg2 run/ss bg2 v fb1 iprg1 sw1 sense1 + pgnd bg1 v fb2 i th2 pgood sw2 sense2 + pgnd 37362 ltc3736egn-2 (note 1) input supply voltage (v in ) ........................ C 0.3v to 10v plllpf, run/ss, sync/fcb, track, sense1 + , sense2 + , iprg1, iprg2 voltages ................. C 0.3v to (v in + 0.3v) v fb1 , v fb2 , i th1 , i th2 voltages .................. C 0.3v to 2.4v sw1, sw2 voltages ............ C2v to v in + 1v or 10v max pgood ..................................................... C 0.3v to 10v tg1, tg2, bg1, bg2 peak output current (<10 s) ..... 1a operating temperature range (note 2) ... C40 c to 85 c storage temperature range .................. C65 c to 125 c junction temperature (note 3) ............................ 125 c lead temperature (soldering, 10 sec) (ltc3736egn-2) .................................................. 300 c
3 ltc3736-2 37362fa parameter conditions min typ max units shutdown threshold at run/ss 0.45 0.65 0.85 v start-up current source run/ss = 0v 0.4 0.7 1 a regulated feedback voltage 0 c to 85 c (note 5) 0.594 0.6 0.606 v C40 c to 85 c 0.591 0.6 0.609 v output voltage line regulation 2.75v < v in < 9.8v (note 5) 0.05 0.2 mv/v output voltage load regulation i th = 0.9v (note 5) 0.12 0.5 % i th = 1.7v C0.12 C0.5 % v fb1,2 input current (note 5) 10 50 na track input current track = 0.6v 10 50 na overvoltage protect threshold measured at v fb 0.66 0.68 0.7 v overvoltage protect hysteresis 20 mv auxiliary feedback threshold sync/fcb ramping positive 0.525 0.6 0.675 v top gate (tg) drive 1, 2 rise time c l = 3000pf 40 ns top gate (tg) drive 1, 2 fall time c l = 3000pf 40 ns bottom gate (bg) drive 1, 2 rise time c l = 3000pf 50 ns bottom gate (bg) drive 1, 2 fall time c l = 3000pf 40 ns maximum current sense voltage ( ? v sense(max) ) iprg = floating 220 240 260 mv (sense + C sw) iprg = 0v 150 167 185 mv iprg = v in 320 345 370 mv soft-start time time for v fb1 to ramp from 0.05v to 0.55v 0.667 0.833 1 ms oscillator and phase-locked loop oscillator frequency unsynchronized (sync/fcb not clocked) plllpf = floating 480 550 600 khz plllpf = 0v 260 300 340 khz plllpf = v in 650 750 825 khz phase-locked loop lock range sync/fcb clocked minimum synchronizable frequency 200 250 khz maximum synchronizable frequency 850 1150 khz phase detector output current sinking f osc > f sync/fcb C4 a sourcing f osc < f sync/fcb 4 a pgood output pgood voltage low i pgood sinking 1ma 125 mv pgood trip level v fb with respect to set output voltage v fb < 0.6v, ramping positive C13 C10.0 C7 % v fb < 0.6v, ramping negative C16 C13.3 C10 % v fb > 0.6v, ramping negative 7 10.0 13 % v fb > 0.6v, ramping positive 10 13.3 16 % electrical characteristics the denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 4.2v unless otherwise specified. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3736e-2 is guaranteed to meet specified performance from 0 c to 85 c. specifications over the C40 c to 85 c operating range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja c/w) note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. note 5: the ltc3736-2 is tested in a feedback loop that servos i th to a specified voltage and measures the resultant v fb voltage. note 6: peak current sense voltage is reduced dependent on duty cycle to a percentage of value as shown in figure 1.
4 ltc3736-2 37362fa typical perfor a ce characteristics uw efficiency and power loss vs load current load step (forced continuous mode) load step (pulse-skipping mode) light load (pulse-skipping mode) tracking start-up with internal soft-start (c ss = 0 f) input voltage (v) 2 C5 normalized frequency shift (%) C4 C2 C1 0 5 2 4 6 7 37368 g08 C3 3 4 1 35 8 9 10 oscillator frequency vs input voltage tracking start-up with external soft-start (c ss = 0.10 f) t a = 25 c unless otherwise noted. load current (ma) 65 efficiency (%) power loss (w) 95 100 60 55 90 75 85 80 70 1 100 1000 10000 37362 g01 50 10 0.01 0.1 1 0.001 10 v out = 2.5v efficiency power loss v in = 3.3v v in = 5v v out ac-coupled 100mv/div v in = 3.3v v out = 1.8v i load = 300ma to 3a sync/fcb = 0v figure 15 circuit 100 s/div 37362 g03 i l 2a/div v out ac-coupled 100mv/div v in = 3.3v v out = 1.8v i load = 300ma to 3a sync/fcb = v in figure 15 circuit 100 s/div 37362 g04 i l 2a/div sw 5v/div v out 50mv/div ac coupled 2.5 s/div v in = 5v v out = 2.5v i load = 300ma sync/fbc = v in figure 15 circuit 37362 g02 i l 2a/div sw 5v/div v out 50mv/div ac coupled 2.5 s/div 37362 g05 i l 2a/div v in = 5v v out = 2.5v i load = 300ma sync/fcb = 0v figure 15 circuit light load (forced continuous mode) v in = 5v r load1 = r load2 = 1 ? figure 15 circuit 200 s/div 37362 g06 500mv/ div v out1 2.5v v out2 1.8v v in = 5v r load1 = r load2 = 1 ? figure 15 circuit 40ms/div 37362 g07 500mv/ div v out1 2.5v v out2 1.8v
5 ltc3736-2 37362fa maximum current sense voltage vs i th pin voltage i th voltage (v) 0.5 C20 current limit (%) 0 20 40 60 100 1 1.5 37362 g09 2 80 forced continuous mode pulse-skipping mode load current (ma) 65 efficiency (%) 95 100 60 55 90 75 85 80 70 1 100 1000 10000 37362 g10 50 10 figure 15 circuit v in = 3.3v v out = 2.5v pulse-skipping mode (sync/fcb = v in ) forced continuous (sync/fcb = 0v) efficiency vs load current regulated feedback voltage vs temperature shutdown (run) threshold vs temperature run/ss pull-up current vs temperature maximum current sense threshold vs temperature temperature ( c) C60 0 run/ss voltage (v) 0.1 0.3 0.4 0.5 1.0 0.7 C20 20 40 37362 g12 0.2 0.8 0.9 0.6 C40 0 60 80 100 temperature ( c) C60 0.4 run/ss pull-up current ( a) 0.5 0.6 0.7 0.8 C20 20 60 100 37362 g13 0.9 1.0 C40 0 40 80 oscillator frequency vs temperature temperature ( c) C60 C10 nromalized frequency (%) C8 C4 C2 0 10 4 C20 20 40 37362 g15 C6 6 8 2 C40 0 60 80 100 temperature ( c) C60 input (v in ) voltage (v) 2.30 2.40 100 37362 g16 2.20 2.10 C20 20 60 C40 0 40 80 2.50 2.25 2.35 2.15 2.45 v in rising v in falling undervoltage lockout threshold vs temperature typical perfor a ce characteristics uw t a = 25 c unless otherwise noted. temperature ( c) C60 150 maximum current sense threshold (mv) 155 160 165 170 C20 20 60 100 37362 g11 175 180 C40 0 40 80 i prg = gnd temperature ( c) C60 feedback voltage (v) 0.600 0.603 0.604 100 37362 g14 0.599 0.598 0.594 C20 20 60 C40 0 40 80 0.596 0.606 0.605 0.602 0.601 0.597 0.595
6 ltc3736-2 37362fa uu u pi fu ctio s i th1 /i th2 (pins 1, 8/pins 4, 11): current threshold and error amplifier compensation point. nominal operating range on these pins is from 0.7v to 2v. the voltage on these pins determines the threshold of the main current comparator. plllpf (pin 3/pin 6): frequency set/pll lowpass filter. when synchronizing to an external clock, this pin serves as the lowpass filter point for the phase-locked loop. nor- mally a series rc is connected between this pin and ground. when not synchronizing to an external clock, this pin serves as the frequency select input. tying this pin to gnd selects 300khz operation; tying this pin to v in selects 750khz op- eration. floating this pin selects 550khz operation. sgnd (pin 4/pin 7): small-signal ground. this pin serves as the ground connection for most internal circuits. v in (pin 5/pin 8): chip signal power supply. this pin pow- ers the entire chip except for the gate drivers. externally fil- tering this pin with a lowpass rc network (e.g., r = 10 ? , c = 1 f) is suggested to minimize noise pickup, especially in high load current applications. track (pin 6/pin 9): tracking input for second control- ler. allows the start-up of v out2 to track that of v out1 ac- cording to a ratio established by a resistor divider on v out1 connected to the track pin. for one-to-one tracking of v out1 and v out2 during start-up, a resistor divider with values equal to those connected to v fb2 from v out2 should be used to connect to track from v out1 . pgood (pin 9/pin 12): power-good output voltage moni- tor open-drain logic output. this pin is pulled to ground when the voltage on either feedback pin (v fb1 , v fb2 ) is not within 13.3% of its nominal set point. pgnd (pins 12, 16, 20, 25/pins 15, 19, 23): power ground. these pins serve as the ground connection for the gate drivers and the negative input to the reverse current com- parators. the exposed pad must be soldered to pcb ground. run/ss (pin 14/pin 17): run control input and optional external soft-start input. forcing this pin below 0.65v shuts down the chip (both channels). driving this pin to v in or releasing this pin enables the chip, using the chips inter- nal soft-start. an external soft-start can be programmed by connecting a capacitor between this pin and ground. tg1/tg2 (pins 17, 15/pins 18, 20): top (pmos) gate drive output. these pins drive the gates of the external p-channel mosfets. these pins have an output swing from pgnd to sense + . sync/fcb (pin 18/pin 21): this pin performs three functions: 1) auxiliary winding feedback input, 2) external clock synchronization input for phase-locked loop, and 3) pulse-skipping operation or forced continuous mode select. for auxiliary winding applications, connect to a shutdown quiescent current vs input voltage input voltage (v) 2 0 shutdown current ( a) 2 6 8 10 20 14 4 6 7 37362 g17 4 16 18 12 35 8 9 10 run/ss = 0v run/ss start-up current vs input voltage input voltage (v) 2 run/ss pin pull-up current ( a) 0.5 0.6 0.7 10 37362 g18 0.4 0.3 0 0.1 4 6 8 3 5 7 9 0.2 0.9 0.8 run/ss = 0v typical perfor a ce characteristics uw t a = 25 c unless otherwise noted. (qfn/ssop package)
7 ltc3736-2 37362fa fu ctio al diagra u u w C + C + C + C + shdn 0.6v v ref extss 0.7 a clk1 clk2 fcb 0.54v v fb1 v fb2 fcb 0.6v slope1 slope2 run/ss v in c vin v in (to controller 1, 2) r vin sync/fcb plllpf undervoltage lockout sync detect voltage controlled oscillator slope comp voltage reference t sec = 1ms intss phase detector pgood shdn ov1 uv1 uv2 ov2 37362 fd (common circuitry) resistor divider from the auxiliary output. to synchronize with an external clock using the pll, apply a cmos compatible clock with a frequency between 250khz and 850khz. to select pulse-skipping operation at light loads, tie this pin to v in . grounding this pin selects forced continuous operation, which allows the inductor current to reverse. when synchronized to an external clock, pulse- skipping operation is enabled at light loads. bg1/bg2 (pins 19, 13/pins 22, 16): bottom (nmos) gate drive output. these pins drive the gates of the external n- channel mosfets. these pins have an output swing from pgnd to sense + . sense1 + /sense2 + (pins 21, 11/pins 24, 14): positive input to differential current comparator. also powers the gate drivers. normally connected to the source of the ex- ternal p-channel mosfet. sw1/sw2 (pins 22, 10/pins 1, 13): switch node connec- tion to inductor. also the negative input to differential peak current comparator and an input to the reverse current com- parator. normally connected to the drain of the external p- channel mosfets, the drain of the external n-channel mosfet, and the inductor. iprg1/iprg2 (pins 23, 2/pins 2, 5): three-state pins to select maximum peak sense voltage threshold. these pins select the maximum allowed voltage drop between the sense + and sw pins (i.e., the maximum allowed drop across the external p-channel mosfet) for each channel. tie to v in , gnd or float to select 345mv, 167mv, or 240mv respectively. v fb1 /v fb2 (pins 24, 7/pins 3, 10): feedback pins. receives the remotely sensed feedback voltage for its controller from an external resistor divider across the output. uu u pi fu ctio s
8 ltc3736-2 37362fa fu ctio al diagra u u w q ov1 clk1 sc1 fcb slope1 sw1 sense1 + irev1 s r rs1 antishoot through pgnd tg1 sense1 + v in v out1 c in c out1 mp1 mn1 bg1 r1b l1 pgnd v fb1 i th1 r ith1 c ith1 0.6v 0.12v sc1 v fb1 sw1 sense1 + r1a C + extss intss eamp shdn C + iprg1 C + icmp C + v fb1 ov1 0.68v + C pgnd irev1 iprog1 fcb sw1 37362 cont1 C + switching logic and blanking circuit scp ricmp ovp (controller 1)
9 ltc3736-2 37362fa fu ctio al diagra u u w (controller 2) q ov2 clk2 sc2 fcb slope2 sw2 sense2 + shdn irev2 s r rs2 antishoot through pgnd sense2 + tg2 sense2 + v in v out2 c out2 mp2 mn2 bg2 r2b r trackb r tracka l2 pgnd v fb2 i th2 track r ith2 c ith2 0.6v 0.12v sc2 track v fb2 sw2 r2a v out1 C + eamp C + C + icmp C + v fb2 ov2 0.68v + C pgnd irev2 fcb sw2 3736 cont2 C + switching logic and blanking circuit ovp scp iprg2
10 ltc3736-2 37362fa main control loop the ltc3736-2 uses a constant frequency, current mode architecture with the two controllers operating 180 de- grees out of phase. during normal operation, the top external p-channel power mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the current comparator (i cmp ) resets the latch. the peak inductor current at which i cmp resets the rs latch is determined by the voltage on the i th pin, which is driven by the output of the error amplifier (eamp). the v fb pin receives the output voltage feedback signal from an exter- nal resistor divider. this feedback signal is compared to the internal 0.6v reference voltage by the eamp. when the load current increases, it causes a slight decrease in v fb relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. while the top p-channel mosfet is off, the bottom n-channel mosfet is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator, i rcmp , or the beginning of the next cycle. shutdown, soft-start and tracking start-up (run/ss and track pins) the ltc3736-2 is shut down by pulling the run/ss pin low. in shutdown, all controller functions are disabled and the chip draws only 9 a. the tg outputs are held high (off) and the bg outputs low (off) in shutdown. releasing run/ss allows an internal 0.7 a current source to charge up the run/ss pin. when the run/ss pin reaches 0.65v, the ltc3736-2s two controllers are enabled. the start-up of v out1 is controlled by the ltc3736-2s internal soft-start. during soft-start, the error amplifier eamp compares the feedback signal v fb1 to the internal soft-start ramp (instead of the 0.6v reference), which rises linearly from 0v to 0.6v in about 1ms. this allows the output voltage to rise smoothly from 0v to its final value, while maintaining control of the inductor current. the 1ms soft-start time can be increased by connecting the optional external soft-start capacitor c ss between the run/ss and sgnd pins. as the run/ss pin continues to operatio u rise linearly from approximately 0.65v to 1.3v (being charged by the internal 0.7 a current source), the eamp regulates the v fb1 proportionally linearly from 0v to 0.6v. the start-up of v out2 is controlled by the voltage on the track pin. when the voltage on the track pin is less than the 0.6v internal reference, the ltc3736-2 regulates the v fb2 voltage to the track pin instead of the 0.6v reference. typically, a resistor divider on v out1 is con- nected to the track pin to allow the start-up of v out2 to track that of v out1 . for one-to-one tracking during start- up, the resistor divider would have the same values as the divider on v out2 that is connected to v fb2 . light load operation (pulse-skipping or continuous conduction) (sync/fcb pin) the ltc3736-2 can be enabled to enter high efficiency pulse-skipping operation or forced continuous conduc- tion mode at low load currents. to select pulse-skipping operation, tie the sync/fcb pin to a dc voltage above 0.6v (e.g., v in ). to select forced continuous operation, tie the sync/fcb to a dc voltage below 0.6v (e.g., sgnd). this 0.6v threshold between pulse-skipping operation and forced continuous mode can be used in secondary wind- ing regulation as described in the auxiliary winding con- trol using sync/fcb pin discussion in the applications information section. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. the p-channel mosfet is turned on every cycle (constant frequency) regardless of the i th pin voltage. in this mode, the efficiency at light loads is lower than in pulse-skipping operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the sync/fcb pin is tied to a dc voltage above 0.6v or when it is clocked by an external clock source to use the phase-locked loop (see frequency selection and phase- locked loop), the ltc3736-2 operates in pwm pulse- skipping mode at light loads. in this mode, the current comparator i cmp may remain tripped for several cycles and (refer to functional diagram)
11 ltc3736-2 37362fa force the external p-channel mosfet to stay off for the same number of cycles. the inductor current is not allowed to reverse, though (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference. however, it provides low current efficiency higher than forced continuous mode. during start-up or a short-circuit condition (v fb1 or v fb2 0.54v), the ltc3736-2 operates in pulse-skipping mode (no current reversal allowed), regardless of the state of the sync/fcb pin. short-circuit protection when an output is shorted to ground (v fb < 0.12v), the switching frequency of that controller is reduced to 1/5 of the normal operating frequency. the other controller is unaffected and maintains normal operation. the short-circuit threshold on v fb2 is based on the smaller of 0.12v and a fraction of the voltage on the track pin. this also allows v out2 to start up and track v out1 more easily. note that if v out1 is truly short-circuited (v out1 = v fb1 = 0v), then the ltc3736-2 will try to regulate v out2 to 0v if a resistor divider on v out1 is connected to the track pin. output overvoltage protection as a further protection, the overvoltage comparator (ov) guards against transient overshoots, as well as other more serious conditions that may overvoltage the output. when the feedback voltage on the v fb pin has risen 13.33% above the reference voltage of 0.6v, the external p-chan- nel mosfet is turned off and the n-channel mosfet is turned on until the overvoltage is cleared. frequency selection and phase-locked loop (plllpf and sync/fcb pins) the selection of switching frequency is a tradeoff between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, operatio u (refer to functional diagram) but requires larger inductance and/or capacitance to main- tain low output ripple voltage. the switching frequency of the ltc3736-2s controllers can be selected using the plllpf pin. if the sync/fcb is not being driven by an external clock source, the plllpf can be floated, tied to v in or tied to sgnd to select 550khz, 750khz or 300khz respectively. a phase-locked loop (pll) is available on the ltc3736-2 to synchronize the internal oscillator to an external clock source that is connected to the sync/fcb pin. in this case, a series rc should be connected between the plllpf pin and sgnd to serve as the plls loop filter. the ltc3736-2 phase detector adjusts the voltage on the plllpf pin to align the turn-on of controller 1s external p-channel mosfet to the rising edge of the synchroniz- ing signal. thus, the turn-on of controller 2s external p-channel mosfet is 180 degrees out of phase with the rising edge of the external clock source. the typical capture range of the ltc3736-2s phase- locked loop is from approximately 200khz to 1mhz, and is guaranteed over temperature to be between 250khz and 850khz. in other words, the ltc3736-2s pll is guaran- teed to lock to an external clock source whose frequency is between 250khz and 850khz. dropout operation when the input supply voltage (v in ) decreases towards the output voltage, the rate of change of the inductor current while the external p-channel mosfet is on (on cycle) decreases. this reduction means that the p-channel mosfet will remain on for more than one oscillator cycle if the inductor current has not ramped up to the threshold set by the eamp on the i th pin. further reduction in the input supply voltage will eventually cause the p-channel mosfet to be turned on 100%, i.e., dc. the output voltage will then be determined by the input voltage minus the voltage drop across the p-channel mosfet and the inductor.
12 ltc3736-2 37362fa operatio u (refer to functional diagram) undervoltage lockout to prevent operation of the external mosfets below safe input voltage levels, an undervoltage lockout is incorporated in the ltc3736-2. when the input supply voltage (v in ) drops below 2.3v, the external p- and n-channel mosfets and all internal circuitry are turned off except for the und- ervoltage block, which draws only a few microamperes. peak current sense voltage selection and slope compensation (iprg1 and iprg2 pins) when a controller is operating below 20% duty cycle, the peak current sense voltage (between the sense + and sw pins) allowed across the external p-channel mosfet is determined by: ? = () v av v sense max ith () C. 07 10 where a is a constant determined by the state of the iprg pins. floating the iprg pin selects a = 1.875; tying iprg to v in selects a = 2.7; tying iprg to sgnd selects a = 1.3. the maximum value of v ith is typically about 1.98v, so the maximum sense voltage allowed across the external p-channel mosfet is 240mv, 345mv, or 167mv for the three respective states of the iprg pin. the peak sense voltages for the two controllers can be independently selected by the iprg1 and iprg2 pins. however, once the controllers duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor given by the curve in figure 1. the peak inductor current is determined by the peak sense voltage and the on-resistance of the external p-channel mosfet: i v r pk sense max ds on = ? () () power-good (pgood) pin a window comparator monitors both feedback voltages and the open-drain pgood output pin is pulled low when either or both feedback voltages are not within 10% of the 0.6v reference voltage. pgood is low when the ltc3736-2 is shut down or in undervoltage lockout. 2-phase operation why the need for 2-phase operation? until recently, con- stant frequency dual switching regulators operated both controllers in phase (i.e., single phase operation). this means that both topside mosfets (p-channel) are turned on at the same time, causing current pulses of up to twice the amplitude of those from a single regulator to be drawn from the input capacitor. these large amplitude pulses increase the total rms current flowing in the input capaci- tor, requiring the use of larger and more expensive input capacitors, and increase both emi and power losses in the input capacitor and input power supply. with 2-phase operation, the two controllers of the ltc3736-2 are operated 180 degrees out of phase. this effectively interleaves the current pulses coming from the topside mosfet switches, greatly reducing the time where they overlap and add together. the result is a significant reduction in the total rms current, which in turn allows the use of smaller, less expensive input capacitors, reduces shielding requirements for emi and improves real world operating efficiency. duty cycle (%) 10 sf = i/i max (%) 60 80 110 100 90 37362 f01 40 20 50 70 90 30 10 0 30 50 70 20 0 40 60 80 100 figure 1. maximum peak current vs duty cycle
13 ltc3736-2 37362fa figure 2 shows example waveforms for a single phase dual controller versus a 2-phase ltc3736-2 system. in this case, 2.5v and 1.8v outputs, each drawing a load current of 2a, are derived from a 7v (e.g., a 2-cell li-ion battery) input supply. in this example, 2-phase operation would reduce the rms input capacitor current from 1.79a rms to 0.91a rms . while this is an impressive reduc- tion by itself, remember that power losses are propor- tional to i rms 2 , meaning that actual power wasted is reduced by a factor of 3.86. the reduced input ripple current also means that less power is lost in the input power path, which could include batteries, switches, trace/connector resistances, and pro- tection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. significant cost and board footprint savings are also realized by being able to use smaller, less expensive, lower rms current-rated input capacitors. of course, the improvement afforded by 2-phase opera- tion is a function of the relative duty cycles of the two controllers, which in turn are dependent upon the input supply voltage. figure 3 depicts how the rms input current varies for single phase and 2-phase dual control- lers with 2.5v and 1.8v outputs over a wide input voltage range. it can be readily seen that the advantages of 2-phase operation are not limited to a narrow operating range, but in fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. operatio u (refer to functional diagram) figure 2. example waveforms for a single phase dual controller vs the 2-phase ltc3736-2 single phase dual controller 2-phase dual controller sw1 (v) sw2 (v) i l1 i l2 i in 37362 f02 input voltage (v) 2 0 input capacitor rms current 0.2 0.6 0.8 1.0 2.0 1.4 4 6 7 37362 f03 0.4 1.6 1.8 1.2 35 8 9 10 single phase dual controler 2-phase dual controler v out1 = 2.5v/2a v out2 = 1.8v/2a figure 3. rms input current comparison
14 ltc3736-2 37362fa the typical ltc3736-2 application circuit is shown in figure 13. external component selection for each of the ltc3736-2s controllers is driven by the load requirement and begins with the selection of the inductor (l) and the power mosfets (mp and mn). power mosfet selection each of the ltc3736-2s two controllers requires two external power mosfets: a p-channel mosfet for the topside (main) switch and an n-channel mosfet for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v br(dss) , threshold voltage v gs(th) , on-resistance r ds(on) , reverse transfer capacitance c rss , turn-off delay t d(off) and the total gate charge q g . the gate drive voltage is the input supply voltage. since the ltc3736-2 is designed for operation down to low input voltages, a sublogic level mosfet (r ds(on) guaranteed at v gs = 2.5v) is required for applications that work close to this voltage. when these mosfets are used, make sure that the input supply to the ltc3736-2 is less than the absolute maximum mosfet v gs rating, which is typically 8v. the p-channel mosfets on-resistance is chosen based on the required load current. the maximum average output load current i out(max) is equal to the peak inductor current minus half the peak-to-peak ripple current i ripple . the ltc3736-2s current comparator monitors the drain- to-source voltage v ds of the p-channel mosfet, which is sensed between the sense + and sw pins. the peak inductor current is limited by the current threshold, set by the voltage on the i th pin of the current comparator. the voltage on the i th pin is internally clamped, which limits the maximum current sense threshold ? v sense(max) to approximately 240mv when iprg is floating (167mv when iprg is tied low; 345mv when iprg is tied high). the output current that the ltc3736-2 can provide is given by: i v r i out max sense max ds on ripple () () () C = ? 2 a reasonable starting point is setting ripple current i ripple to be 40% of i out(max) . rearranging the above equation yields: r v i ds on max sense max out max ()( ) () () ? = ? 5 6 for duty cycle < 20%. however, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of r ds(on) to provide the required amount of load current: rsf v i ds on max sense max out max ()( ) () () ?? = ? 5 6 where sf is a scale factor whose value is obtained from the curve in figure 1. these must be further derated to take into account the significant variation in on-resistance with temperature. the following equation is a good guide for determin- ing the required r ds(on)max at 25 c (manufacturers specification), allowing some margin for variations in the ltc3736-2 and external component values: rsf v i ds on max sense max out max t ()( ) () () ?.? ? ? = ? 5 6 09 the t is a normalizing term accounting for the tempera- ture variation in on-resistance, which is typically about 0.4%/ c, as shown in figure 4. junction to case tempera- ture t jc is about 10 c in most applications. for a maxi- mum ambient temperature of 70 c, using 80 c ~ 1.3 in the above equation is a reasonable choice. the power dissipated in the top and bottom mosfets strongly depends on their respective duty cycles and load current. when the ltc3736-2 is operating in continuous mode, the duty cycles for the mosfets are: top p-channel duty cycle = v bottom n-channel duty cycle = v out in v v v in out in C applicatio s i for atio wu uu
15 ltc3736-2 37362fa the mosfet power dissipations at maximum output current are: p v v irv icf p vv v ir top out in out max t ds on in out max rss osc bot in out in out max t ds on =+ = ??? ? ??? C ??? () () () () () 22 2 2 r r both mosfets have i 2 r losses and the p top equation includes an additional term for transition losses, which are largest at high input voltages. the bottom mosfet losses are greatest at high input voltage or during a short-circuit when the bottom duty cycle is nearly 100%. the ltc3736-2 utilizes a nonoverlapping, antishoot- through gate drive control scheme to ensure that the p- and n-channel mosfets are not turned on at the same time. to function properly, the control scheme requires that the mosfets used are intended for dc/dc switching applications. many power mosfets, particularly p-chan- nel mosfets, are intended to be used as static switches and therefore are slow to turn on or off. reasonable starting criteria for selecting the p-channel mosfet are that it must typically have a gate charge (q g ) less than 25nc to 30nc (at 4.5v gs ) and a turn-off delay (t d(off) ) of less than approximately 140ns. however, due to differences in test and specification methods of various mosfet manufacturers, and in the variations in q g and t d(off) with gate drive (v in ) voltage, the p-channel mosfet ultimately should be evaluated in the actual ltc3736-2 application circuit to ensure proper operation. shoot-through between the p-channel and n-channel mosfets can most easily be spotted by monitoring the input supply current. as the input supply voltage in- creases, if the input supply current increases dramatically, then the likely cause is shoot-through. note that some mosfets that do not work well at high input voltages (e.g., v in > 5v) may work fine at lower voltages (e.g., 3.3v). table 1 shows a selection of p-channel mosfets from different manufacturers that are known to work well in ltc3736-2 applications. selecting the n-channel mosfet is typically easier, since for a given r ds(on) , the gate charge and turn-on and turn- off delays are much smaller than for a p-channel mosfet. table 1. selected p-channel mosfets suitable for ltc3736-2 applications part number manufacturer type package si7540dp siliconix complementary powerpak p/n so-8 si9801dy siliconix complementary so-8 p/n fdw2520c fairchild complementary tssop-8 p/n fdw2521c fairchild complementary tssop-8 p/n si3447bdv siliconix single p tsop-6 si9433bdy siliconix single p so-8 fdc602p fairchild single p tsop-6 fdc606p fairchild single p tsop-6 fdc638p fairchild single p tsop-6 fdw2502p fairchild dual p tssop-8 fds6875 fairchild dual p so-8 hat1054r hitachi dual p so-8 ntmd6p02r2-d on semi dual p so-8 applicatio s i for atio wu uu junction temperature ( c) C50 t normalized on resistance 1.0 1.5 150 37362 f04 0.5 0 0 50 100 2.0 figure 4. r ds(on) vs temperature
16 ltc3736-2 37362fa operating frequency and synchronization the choice of operating frequency, f osc , is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switch- ing losses, both gate charge loss and transition loss. however, lower frequency operation requires more induc- tance for a given amount of ripple current. the internal oscillator for each of the ltc3736-2s control- lers runs at a nominal 550khz frequency when the plllpf pin is left floating and the sync/fcb pin is a dc low or high. pulling the plllpf to v in selects 750khz operation; pulling the plllpf to gnd selects 300khz operation. alternatively, the ltc3736-2 will phase-lock to a clock signal applied to the sync/fcb pin with a frequency between 250khz and 850khz (see phase-locked loop and frequency synchronization). inductor value calculation given the desired input and output voltages, the inductor value and operating frequency f osc directly determine the inductors peak-to-peak ripple current: i v v vv fl ripple out in in out osc = ? ? ? ? ? ? C ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l vv fi v v in out osc ripple out in C ? ? inductor core selection once the inductance value is determined, the type of inductor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance re- quires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design cur- rent is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! schottky diode selection (optional) the schottky diodes d1 and d2 in figure 16 conduct current during the dead time between the conduction of the power mosfets . this prevents the body diode of the bottom n-channel mosfet from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. a 1a schottky diode is generally a good size for most ltc3736-2 applications, since it conducts a relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. this diode may be omitted if the efficiency loss can be tolerated. c in and c out selection the selection of c in is simplified by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the control- ler with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms applicatio s i for atio wu uu
17 ltc3736-2 37362fa capacitor current requirement. increasing the output cur- rent drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c i v vvv in max in out in out required i rms ()( ) [] C / 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3736-2, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of the ltc3736-2 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse re- sistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall benefit of a multiphase design will only be fully realized when the source imped- ance of the power supply/battery is included in the effi- ciency testing. the sources of the p-channel mosfets should be placed within 1cm of each other and share a common c in (s). separating the sources and c in may pro- duce undesirable voltage and current resonances at v in . a small (0.1 f to 1 f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3736-2, is also suggested. a 10 ? resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( ? v out ) is approximated by: ? + ? ? ? ? ? ? v i esr fc out ripple out 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. setting output voltage the ltc3736-2 output voltages are each set by an external feedback resistor divider carefully placed across the out- put, as shown in figure 5. the regulated output voltage is determined by: vv r r out b a =+ ? ? ? ? ? ? 06 1 .? to improve the frequency response, a feedforward capaci- tor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. applicatio s i for atio wu uu
18 ltc3736-2 37362fa this can be increased by placing a capacitor between the run/ss pin and sgnd. in this case, the soft-start time will be approximately: tc mv a ss ss 1 600 07 = ? . tracking the start-up of v out2 is controlled by the voltage on the track pin. normally this pin is used to allow the start-up of v out2 to track that of v out1 as shown qualitatively in figures 7a and 7b. when the voltage on the track pin is less than the internal 0.6v reference, the ltc3736-2 regulates the v fb2 voltage to the track pin voltage instead of 0.6v. the start-up of v out2 may ratiometrically track that of v out1 , according to a ratio set by a resistor divider (figure 7c): v v ra r rr rb ra out out tracka tracka trackb 1 2 2 22 = + + ? for coincident tracking (v out1 = v out2 during start-up), r2a = r tracka r2b = r trackb the ramp time for v out2 to rise from 0v to its final value is: tt r ra ra rb rr ss ss tracka tracka trackb 21 1 11 = + + ?? applicatio s i for atio wu uu 3.3v or 5v run/ss run/ss c ss c ss (internal soft-start) d1 37362 f06 v dd v in run/ss figure 6. run/ss pin interfacing 1/2 ltc3736-2 v fb v out r b c ff r a 37362 f05 figure 5. setting output voltage run/soft-start function the run/ss pin is a dual purpose pin that provides the optional external soft-start function and a means to shut down the ltc3736-2. pulling the run/ss pin below 0.65v puts the ltc3736-2 into a low quiescent current shutdown mode (i q = 9 a). if run/ss has been pulled all the way to ground, there will be a delay before the ltc3736-2 comes out of shutdown and is given by: tv c a sfc delay ss ss = = 065 07 093 .? . ./? this pin can be driven directly from logic as shown in figure 6. diode d1 in figure 6 reduces the start delay but allows c ss to ramp up slowly providing the soft-start function. this diode (and capacitor) can be deleted if the external soft-start is not needed. during soft-start, the start-up of v out1 is controlled by slowly ramping the positive reference to the error amplifier from 0v to 0.6v, allowing v out1 to rise smoothly from 0v to its final value. the default internal soft-start time is 1ms. ltc3736-2 v fb2 v out2 v out1 v fb1 track r2b r2a 37362 f07a r1b r1a r tracka r trackb figure 7a. using the track pin
19 ltc3736-2 37362fa for coincident tracking, tt v v ss ss out f out f 21 2 1 = ? where v out1f and v out2f are the final, regulated values of v out1 and v out2 . v out1 should always be greater than v out2 when using the track pin. if no tracking function is desired, then the track pin may be tied to v in . how- ever, in this situation there would be no (internal nor external) soft-start on v out2 . phase-locked loop and frequency synchronization the ltc3736-2 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (vco) and a phase detector. this allows the turn-on of the external p- channel mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the sync/fcb pin. the turn-on of controller 2s external p-channel mosfet is thus 180 degrees out of phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen- tary current sources that charge or discharge the external filter network connected to the plllpf pin. the relation- ship between the voltage on the plllpf pin and operating frequency, when there is a clock signal applied to sync/ fcb, is shown in figure 8 and specified in the electrical characteristics table. note that the ltc3736-2 can only be synchronized to an external clock whose frequency is within range of the ltc3736-2s internal vco, which is nominally 200khz to 1mhz. this is guaranteed, over temperature and variations, to be between 300khz and 750khz. a simplified block diagram is shown in figure 9. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced con- tinuously from the phase detector output, pulling up the plllpf pin. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the applicatio s i for atio wu uu time (7b) coincident tracking v out1 v out2 output voltage time 37362 f07b,c (7c) ratiometric tracking v out1 v out2 output voltage figures 7b and 7c. two different modes of output voltage tracking plllpf pin voltage (v) 0 0 frequency (khz) 0.5 1 1.5 2 37362 f08 2.4 200 400 600 800 1000 1200 1400 figure 8. relationship between oscillator frequency and voltage at the plllpf pin when synchronizing to an external clock
20 ltc3736-2 37362fa applicatio s i for atio wu uu plllpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the plllpf pin is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor c lp holds the voltage. the loop filter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01 f. typically, the external clock (on sync/fcb pin) input high level is 1.6v, while the input low level is 1.2v. table 2 summarizes the different states in which the plllpf pin can be used. table 2 plllpf pin sync/fcb pin frequency 0v dc voltage 300khz floating dc voltage 550khz v in dc voltage 750khz rc loop filter clock signal phase-locked to external clock auxiliary winding control using sync/fcb pin the sync/fcb can be used as an auxiliary feedback to provide a means of regulating a flyback winding output. when this pin drops below its ground-referenced 0.6v threshold, continuous mode operation is forced. during continuous mode, current flows continuously in the transformer primary. the auxiliary winding draws current only when the bottom, synchronous n-channel mosfet is on. when primary load currents are low and/or the v in /v out ratio is close to unity, the synchronous mosfet may not be on for a sufficient amount of time to transfer power from the output capacitor to the auxiliary load. forced continuous operation will support an auxil- iary winding as long as there is a sufficient synchronous mosfet duty factor. the fcb input pin removes the requirement that power must be drawn from the trans- former primary in order to extract power from the auxiliary winding. with the loop in continuous mode, the auxiliary output may nominally be loaded without regard to the primary output load. the auxiliary output voltage v aux is normally set as shown in figure 10 by the turns ratio n of the transformer: v aux ? (n + 1) v out however, if the controller goes into pulse-skipping op- eration and halts switching due to a light primary load current, then v aux will droop. an external resistor divider from v aux to the fcb sets a minimum voltage v aux(min) : vv r r aux min () . =+ ? ? ? ? ? ? 06 1 6 5 digital phase/ frequency detector oscillator 2.4v r lp c lp 37362 f09 plllpf external oscillator sync/ fcb figure 9. phase-locked loop block diagram
21 ltc3736-2 37362fa applicatio s i for atio wu uu if v aux drops below this value, the fcb voltage forces temporary continuous switching operation until v aux is again above its minimum. table 3 summarizes the different states in which the sync/fcb pin can be used table 3 sync/fcb pin condition 0v to 0.5v forced continuous mode current reversal allowed 0.7v to v in pulse-skipping operation enabled no current reversal allowed feedback resistors regulate an auxiliary winding external clock signal enable phase-locked loop (synchronize to external clk) pulse-skipping at light loads no current reversal allowed fault condition: short-circuit and current limit to prevent excessive heating of the bottom mosfet, foldback current limiting can be added to reduce the current in proportion to the severity of the fault. foldback current limiting is implemented by adding di- odes d fb1 and d fb2 between the output and the i th pin as shown in figure 11. in a hard short (v out = 0v), the current will be reduced to approximately 50% of the maximum output current. low supply operation although the ltc3736-2 can function down to below 2.4v, the maximum allowable output current is reduced as v in decreases below 3v. figure 12 shows the amount of change as the supply is reduced down to 2.4v. also shown is the effect on v ref . minimum on-time considerations minimum on-time, t on(min) , is the smallest amount of time that the ltc3736-2 is capable of turning the top p-channel mosfet on and then off. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle and high frequency applications may approach the minimum on-time limit and care should be taken to ensure that: t v fv on min out osc in () ? < if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc3736-2 will begin to skip cycles (unless forced continuous mode is selected). the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on- time for the ltc3736-2 is typically about 200ns. how- ever, as the peak sense voltage (i l(peak) ? r ds(on) ) decreases, the minimum on-time gradually increases up to about 250ns. this is of particular concern in forced continuous applications with low ripple current at light + 1/2 ltc3736-2 v fb i th r2 d fb1 v out d fb2 37362 f11 r1 figure 11. foldback current limiting input voltage (v) 75 normalized voltage or current (%) 85 95 105 80 90 100 2.2 2.4 2.6 2.8 37362 f12 3.0 2.1 2.0 2.3 2.5 2.7 2.9 v ref maximum sense voltage figure 12. line regulation of v ref and maximum sense voltage for low input supply ltc3736-2 + + r6 r5 1 f v out v aux c out l1 1:n sync/fcb bg sw tg 37362 f10 v in figure 10. auxiliary output loop connection
22 ltc3736-2 37362fa loads. if forced con tinuous mode is selected and the duty cycle falls below the minimum on-time requirement, the output will be regulated by overvoltage protection. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in ltc3736-2 circuits: 1) ltc3736-2 dc bias current, 2) mosfet gate charge current, 3) i 2 r losses, and 4) transition losses. 1) the v in (pin) current is the dc supply current, given in the electrical characteristics, excluding mosfet driver currents. v in current results in a small loss that in- creases with v in . 2) mosfet gate charge current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from sense + to ground. the resulting dq/dt is a current out of sense + , which is typically much larger than the dc supply current. in continuous mode, i gatechg = f ? q p . 3) i 2 r losses are calculated from the dc resistances of the mosfets and inductor. in continuous mode, the aver- age output current flows through l but is chopped between the top p-channel mosfet and the bottom n-channel mosfet. the mosfet r ds(on) s multiplied by duty cycle can be summed with the resistance of l to obtain i 2 r losses. 4) transition losses apply to the top external p-channel mosfet and increase with higher operating frequen- cies and input voltages. transition losses can be esti- mated from: transition loss = 2 (v in ) 2 i o(max) c rss (f) other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( ? i load )(esr), where esr is the effective series resistance of c out . ? i load also begins to charge or dis- charge c out , which generates a feedback error signal. the regulator loop then returns v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing. opti-loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the i th series r c -c c filter (see functional diagram) sets the dominant pole-zero loop compensation. the i th exter- nal components shown in the typical application on the front page of this data sheet will provide an adequate starting point for most applications. the values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability. the gain of the loop will be increased by increasing r c , and the bandwidth of the loop will be applicatio s i for atio wu uu opti-loop is a registered trademark of linear technology corporation.
23 ltc3736-2 37362fa increased by decreasing c c . the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(c load ). thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3736-2. these items are illustrated in the layout dia- gram of figure 13. figure 14 depicts the current wave- forms present in the various branches of the 2-phase dual regulator. 1) the power loop (input capacitor, mosfets, inductor, output capacitor) of each channel should be as small as possible and isolated as much as possible from the power loop of the other channel. ideally, the drains of the p- and n-channel fets should be connected close to one another with an input capacitor placed across the fet sources (from the p-channel source to the n- channel source) right at the fets. it is better to have two separate, smaller valued input capacitors (e.g., two 10 fone for each channel) than it is to have a single larger valued capacitor (e.g., 22 f) that the channels share with a common connection. 2) the signal and power grounds should be kept separate. the signal ground consists of the feedback resistor dividers, i th compensation networks and the sgnd pin. the power grounds consist of the (C) terminal of the input and output capacitors and the source of the n- channel mosfet. each channel should have its own power ground for its power loop (as described above in item 1). the power grounds for the two channels should connect together at a common point. it is most important to keep the ground paths with high switch- ing currents away from each other. the pgnd pins on the ltc3736-2 ic should be shorted together and connected to the common power ground connection (away from the switching currents). 3) put the feedback resistors close to the v fb pins. the trace connecting the top feedback resistor (r b ) to the output capacitor should be a kelvin trace. the i th compensation components should also be very close to the ltc3736-2. 4) the current sense traces (sense + and sw) should be kelvin connections right at the p-channel mosfet source and drain. 5) keep the switch nodes (sw1, sw2) and the gate driver nodes (tg1, tg2, bg1, bg2) away from the small- signal components, especially the opposite channels feedback resistors, i th compensation components, and the current sense pins (sense + and sw). applicatio s i for atio wu uu sw1 iprg1 v fb1 i th1 iprg2 plllpf sgnd v in track v fb2 i th2 pgood sense1 + pgnd bg1 sync/fcb tg1 pgnd tg2 run/ss bg2 pgnd sense2 + sw2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ltc3736egn-2 + + c out1 c out2 c vin1 c vin v out1 v out2 bold lines indicate high current paths 37362 f13 l1 l2 mn1 mp1 mn2 mp2 v in c vin2 figure 13. ltc3736-2 layout diagram
24 ltc3736-2 37362fa r l1 l1 mp1 v out1 c out1 mn1 mn2 + v in c in r in + r l2 bold lines indicate high, switching current lines. keep lines to a minimum length l2 mp2 37362 f14 v out2 c out2 + applicatio s i for atio wu uu figure 14. branch current waveforms
25 ltc3736-2 37362fa typical applicatio s u figure 16. 2-phase, 750khz, dual output synchronous dc/dc converter sgnd plllpf iprg2 iprg1 v fb1 i th1 sw1 r vin 10 ? r ith2 22k c ith2 1000pf c ss 10nf c in 22 f c vin 1 f v in 3.3v v in c ith2a 100pf r ith1 22k c ith1 1000pf c ith1a 100pf r fb1b 187k r fb1a 59k pgood v fb2 track pgnd i th2 tg2 ltc3736euf-2 pgnd tg1 sync/fcb bg1 pgnd 22 21 20 19 18 17 16 15 14 13 12 11 10 25 23 24 1 2 3 4 5 9 8 7 6 sense1 + mp1 si3447bdv mp2 si3447bdv l1 1.5 h l2 1.5 h mn1 si3460dv mn2 si3460dv run/ss bg2 pgnd sw2 sense2 + r trackb 118k r tracka 59k r fb2a 59k r fb2b 118k c out2 47 f 2 c out1 47 f 2 d1 v out1 2.5v 4a v out2 1.8v 4a 37362 f16 c ff1 22pf l1, l2: vishay ihlp-2525cz-01 d1, d2: optional d2 figure 15. 2-phase, 550khz, dual output synchronous dc/dc converter sgnd plllpf iprg2 iprg1 v fb1 i th1 sw1 r vin 10 ? r ith2 15k c ith2 220pf c ss 10nf c in 10 f 2 c vin 1 f v in 5v v in c ith2b 100pf r ith1 15k c ith1 220pf c ith1a 100pf r fb1b 187k r fb1a 59k pgood v fb2 track 25 i th2 tg2 ltc3736euf-2 pgnd tg1 sync/fcb bg1 pgnd 22 21 20 19 18 17 16 15 14 13 12 11 10 23 24 1 2 3 4 5 9 8 7 6 sense1 + mp1 mp2 l1 1.5 h l2 1.5 h mn1 si7540dp mn2 si7540dp run/ss bg2 pgnd pgnd sw2 sense2 + r trackb 118k r tracka 59k r fb2a 59k r fb2b 118k c out2 150 f c out1 150 f v out1 2.5v 6a v out2 1.8v 6a 37362 f15 + +
26 ltc3736-2 37362fa figure 17. 2-phase, synchronizable, dual output synchronous dc/dc converter sgnd plllpf iprg2 iprg1 v fb1 i th1 sw1 r vin 10 ? r ith2 22k c ith2 1nf c in 22 f c vin 1 f v in 3.3v v in r ith1 22k c ith1 1nf c ff1 100pf c ff1 100pf c lp 10nf r lp 15k r fb1b 187k r fb1a 59k pgood v fb2 track i th2 tg2 ltc3736egn-2 pgnd tg1 sync/fcb bg1 pgnd 1 24 23 22 21 20 19 18 17 16 15 14 13 l1, l2: vishay ihlp-2525cz-01 2 3 4 5 6 7 5 12 11 10 9 sense1 + mp1 sw1 sw2 clk in mp2 l1 1.5 h l2 1.5 h mn1 si7540dp mn2 si7540dp run/ss bg2 pgnd sw2 sense2 + r trackb 118k r tracka 59k r fb2a 59k r fb2b 118k c out2 100 f c out1 100 f v out1 2.5v 5a v out2 1.8v 5a 37362 f17 typical applicatio s u
27 ltc3736-2 37362fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) u package descriptio 4.00 0.10 (4 sides) 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)to be approved 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present pin 1 top mark (note 5) 0.38 0.10 24 0.23 typ (4 sides) 23 1 2 bottom viewexposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf24) qfn 0603 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline g24 ssop 0204 0.09 C 0.25 (.0035 C .010) 0 C 8 0.55 C 0.95 (.022 C .037) 5.00 C 5.60** (.197 C .221) 7.40 C 8.20 (.291 C .323) 1234 5 6 7 8 9 10 11 12 7.90 C 8.50* (.311 C .335) 21 22 18 17 16 15 14 13 19 20 23 24 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 C 0.38 (.009 C .015) typ millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** 0.42 0.03 0.65 bsc 5.3 C 5.7 7.8 C 8.2 recommended solder pad layout 1.25 0.12 gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641)
28 ltc3736-2 37362fa part number description comments ltc1735 high efficiency synchronous step-down controller burst mode operation, 16-pin narrow ssop, 3.5v v in 36v ltc1778 no r sense tm synchronous step-down controller current mode operation without sense resistor, fast transient response, 4v v in 36v ltc2923 power supply tracking controller controls up to three supplies, 10-lead msop ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, i q = 60 a, i sd = <1 a, ms package ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.25v to 5.5v, i sd = <1 a, with output tracking tssop-20e package ltc3418 8a, 4mhz synchronous step-down regulator v in : 2.25v to 5.5v, 5mm 7mm qfn package ltc3701 2-phase, low input voltage dual step-down dc/dc controller 2.5v v in 9.8v, 550khz, pgood, pll, 16-lead ssop ltc3708 fast 2-phase, no r sense buck controller with output tracking constant on-time dual controller, v in up to 36v, very low duty cycle operation, 5mm 5mm qfn package ltc3728/ltc3728l dual, 550khz, 2-phase synchronous step-down constant frequency, v in to 36v, 5v and 3.3v ldos, switching regulator 5mm 5mm qfn or 28-lead ssop ltc3736 dual, 2-phase, no r sense synchronous controller 2.75v v in 9.8v, output tracking ltc3736-1 dual, 2-phase, no r sense synchronous controller with v in : 2.75v to 9.8v, 4mm 4mm qfn package spread spectrum spread spectrum operation; output tracking ltc3737 dual, 2-phase, no r sense controller with non-synchronous constant frequency with pll, 4mm 4mm output tracking qfn and 24-lead ssop packages ltc3772 no r sense step-down dc/dc controller 2.75v v in 9.8v, sot-23 or 3mm 2mm dfn packages ltc3776 dual, 2-phase, no r sense synchronous controller for provides v ddq and v tt with one ic, 2.75v v in 9.8v, ddr/qdr memory termination 4mm 4mm qfn and 24-lead ssop packages ltc3808 no r sense , low emi, synchronous step-down controller with 2.75v v in 9.8v; spread spectrum operation; 3mm 4mm output tracking dfn and 16-lead ssop packages ltc3809/ltc3809-1 no r sense synchronous step-down controllers 2.75v to 9.8v, 3mm 3mm dfn and 10-lead msope packages no r sense is a trademark of linear technology corporation. lt 0206 rev a ? printed in usa ? linear technology corporation 2005 related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com typical applicatio u 2-phase, 750khz, dual output synchronous dc/dc converter sgnd plllpf iprg2 iprg1 v fb1 i th1 sw1 r vin 10 ? r ith2 22k c ith2 1000pf c ss 10nf c in 22 f c vin 1 f v in 3.3v v in c ith2a 100pf r ith1 22k c ith1 1000pf c ith1a 100pf r fb1b 187k r fb1a 59k pgood v fb2 track pgnd i th2 tg2 ltc3736euf-2 pgnd tg1 sync/fcb bg1 pgnd 22 21 20 19 18 17 16 15 14 13 12 11 10 25 23 24 1 2 3 4 5 9 8 7 6 sense1 + mp1 si3447bdv mp2 si3447bdv l1 1.5 h l2 1.5 h mn1 si3460dv mn2 si3460dv run/ss bg2 pgnd sw2 sense2 + r trackb 118k r tracka 59k r fb2a 59k r fb2b 118k c out2 47 f 2 c out1 47 f 2 d1 v out1 2.5v 4a v out2 1.8v 4a 37362 f16 c ff1 22pf l1, l2: vishay ihlp-2525cz-01 d1, d2: optional d2

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